module ysyx_050369_axi_arbiter (
    input       clk,
    input       rst,
    //ifu
    output  [127:0] o_ic_cache_wdata,
    output          o_ic_cache_wen,
    input           i_ic_axi_read,
    input           i_ic_unbrust,
    input   [31 :0] i_ic_raddr,
	input   [2:0]   i_dc_size_t,
    input           i_dc_axi_read ,
    input           i_dc_unbrust,
    input           i_dc_uncache,
    input   [31:0]  i_dc_raddr,
    input   [31:0]  i_dc_waddr,
    input   [7 :0]  i_dc_wstrb_t,
    input  			i_dc_axi_write,
    input  [31:0]   i_dc_dirty_addr,
    input  	[127:0] i_dc_wdata,
    output  [127:0] o_dc_axi_data,
    output          o_dc_axi_wen ,
    output          o_dc_wdone,
    output          o_dc_rdone,
// slave
    //read addr
    input         i_sl_arready,
    output        o_sl_arvalid,
    output  [31:0]o_sl_araddr,
    output  [3:0] o_sl_arid,
    output  [7:0] o_sl_arlen,
    output  [2:0] o_sl_arsize,
    output  [1:0] o_sl_arburst,
    //read data
    output        o_sl_rready,
    input         i_sl_rvalid,
    input [1:0]   i_sl_rresp,
    input [63:0]  i_sl_rdata,
    input         i_sl_rlast,
    input [3:0]   i_sl_rid,
    //write addr
    input         i_sl_awready,
    output        o_sl_awvalid,
    output  [31:0]o_sl_awaddr,
    output  [3:0] o_sl_awid,
    output  [7:0] o_sl_awlen,
    output  [2:0] o_sl_awsize,
    output  [1:0] o_sl_awburst,
    //write data
    input         i_sl_wready,
    output        o_sl_wvalid,
    output [63:0] o_sl_wdata,
    output [7:0]  o_sl_wstrb,
    output        o_sl_wlast,
    //write res
    output        o_sl_bready,
    input         i_sl_bvalid,
    input  [1:0]  i_sl_bresp,
    input  [3:0]  i_sl_bid
);
reg ic_axi_read_r;
wire ic_axi_read_v;
always @(posedge clk ) begin
    if (rst) begin
        ic_axi_read_r <= 'b0;
    end
    else ic_axi_read_r <= i_ic_axi_read;
end
assign ic_axi_read_v = i_ic_axi_read || ic_axi_read_r;
	wire  [2:0]  size_t;
    wire         axi_read ;
    wire         unbrust;
    wire         uncache;
    wire  [31:0] raddr;
    wire  [31:0] waddr;
    wire  [7 :0] wstrb_t;
    wire  	     axi_write;
    wire  [31:0] dirty_addr;
    wire  [127:0]wdata;
    wire  [127:0]axi_data;
    wire         axi_wen ;
    wire         wdone;
    wire         rdone;
    assign axi_read         =   i_ic_axi_read || i_dc_axi_read;
	assign size_t           =   ic_axi_read_v ? 3'b010        : i_dc_size_t;
    assign unbrust          =   ic_axi_read_v ? i_ic_unbrust  : i_dc_unbrust;
    assign uncache          =   ic_axi_read_v ? 1'b0          : i_dc_uncache;
    assign raddr            =   ic_axi_read_v ? i_ic_raddr    : i_dc_raddr;
    assign o_ic_cache_wdata =   ic_axi_read_v ? axi_data : 'b0;
    assign o_ic_cache_wen   =   ic_axi_read_v && axi_wen  ;
    assign o_dc_axi_data    =   ic_axi_read_v ? 'b0 : axi_data ;
    assign o_dc_axi_wen     =   i_dc_axi_read && ~ic_axi_read_v&& axi_wen;

    assign waddr            =   ic_axi_read_v ?'b0 :i_dc_waddr;
    assign wstrb_t          =   ic_axi_read_v ?'b0 :i_dc_wstrb_t;
    assign axi_write        =   ic_axi_read_v ?'b0 :i_dc_axi_write;
    assign dirty_addr       =   ic_axi_read_v ?'b0 :i_dc_dirty_addr;
    assign wdata            =   ic_axi_read_v ?'b0 :i_dc_wdata;

    assign o_dc_wdone       =   ~ic_axi_read_v &&wdone    ;
    assign o_dc_rdone       =   ~ic_axi_read_v &&rdone    ;
ysyx_050369_cache2axi cache2axi(
	.clk		(clk),    // Clock
	.rst		(rst),  // Asynchronous reset active low
	.size_t     (size_t),
    .axi_read 	(axi_read),
    .unbrust	(unbrust),
    .uncache	(uncache),
    .i_raddr	(raddr),
    .axi_write	(axi_write),
    .dirty_addr	(dirty_addr),
	.i_waddr	(waddr),
    .i_wdata  	(wdata),
	.wstrb_t	(wstrb_t),
	.wdone		(wdone),
    .rdone		(rdone),
	.cache_wdata(axi_data),
    .wen 		(axi_wen),

    .i_awready  (i_sl_awready),              
    .o_awvalid  (o_sl_awvalid),
    .o_awaddr   (o_sl_awaddr),
    .o_awid     (o_sl_awid),
    .o_awlen    (o_sl_awlen),
    .o_awsize   (o_sl_awsize),
    .o_awburst  (o_sl_awburst),
    .i_wready   (i_sl_wready),                
    .o_wvalid   (o_sl_wvalid),
    .o_wdata    (o_sl_wdata),
    .o_wstrb    (o_sl_wstrb),    
    .o_wlast    (o_sl_wlast),
    .o_bready   (o_sl_bready),                
    .i_bvalid   (i_sl_bvalid),
    .i_bresp    (i_sl_bresp),                 
    .i_bid      (i_sl_bid),
    .i_arready  (i_sl_arready),                  
    .o_arvalid  (o_sl_arvalid),   
    .o_araddr   (o_sl_araddr),
    .o_arid     (o_sl_arid),
    .o_arlen    (o_sl_arlen),
    .o_arsize   (o_sl_arsize),
    .o_arburst  (o_sl_arburst),
    .o_rready   (o_sl_rready),                  
    .i_rvalid   (i_sl_rvalid),                
    .i_rresp    (i_sl_rresp),
    .i_rdata    (i_sl_rdata),
    .i_rlast    (i_sl_rlast),
    .i_rid      (i_sl_rid)

);
/////////////////////////////////////////////
/////////////////////////////////////////////
//     wire          ic_awready   ;             
//     wire          ic_awvalid   ;
//     wire [31:0]   ic_awaddr    ;
//     wire [3:0]    ic_awid      ;
//     wire [7:0]    ic_awlen     ;
//     wire [2:0]    ic_awsize    ;
//     wire [1:0]    ic_awburst   ;
//     wire          ic_wready    ;                
//     wire          ic_wvalid    ;
//     wire [63:0]   ic_wdata     ;
//     wire [7:0]    ic_wstrb     ;
//     wire          ic_wlast     ;
//     wire          ic_bready    ;                
//     wire          ic_bvalid    ;
//     wire [1:0]    ic_bresp     ;                     
//     wire [3:0]    ic_bid       ;
//     wire          ic_arready   ;                
//     wire          ic_arvalid   ;
//     wire [31:0]   ic_araddr    ;
//     wire [3:0]    ic_arid      ;
//     wire [7:0]    ic_arlen     ;
//     wire [2:0]    ic_arsize    ;
//     wire [1:0]    ic_arburst   ;
//     wire          ic_rready    ;                 
//     wire          ic_rvalid    ;                
//     wire [1:0]    ic_rresp     ;
//     wire [63:0]   ic_rdata     ;
//     wire          ic_rlast     ;
//     wire [3:0]    ic_rid       ;
//     wire          dc_awready   ;             
//     wire          dc_awvalid   ;
//     wire [31:0]   dc_awaddr    ;
//     wire [3:0]    dc_awid      ;
//     wire [7:0]    dc_awlen     ;
//     wire [2:0]    dc_awsize    ;
//     wire [1:0]    dc_awburst   ;
//     wire          dc_wready    ;                
//     wire          dc_wvalid    ;
//     wire [63:0]   dc_wdata     ;
//     wire [7:0]    dc_wstrb     ;
//     wire          dc_wlast     ;
//     wire          dc_bready    ;                
//     wire          dc_bvalid    ;
//     wire [1:0]    dc_bresp     ;                     
//     wire [3:0]    dc_bid       ;
//     wire          dc_arready   ;                
//     wire          dc_arvalid   ;
//     wire [31:0]   dc_araddr    ;
//     wire [3:0]    dc_arid      ;
//     wire [7:0]    dc_arlen     ;
//     wire [2:0]    dc_arsize    ;
//     wire [1:0]    dc_arburst   ;
//     wire          dc_rready    ;                 
//     wire          dc_rvalid    ;                
//     wire [1:0]    dc_rresp     ;
//     wire [63:0]   dc_rdata     ;
//     wire          dc_rlast     ;
//     wire [3:0]    dc_rid       ;
// /////////////////////////////////////////////////
// /////////////////////////////////////////////////


// ysyx_050369_cache2axi icache2axi(
// 	.clk		(clk),    // Clock
// 	.rst		(rst),  // Asynchronous reset active low
// 	.size_t		(3'b010),
//     .axi_read 	(i_ic_axi_read),
//     .unbrust	(i_ic_unbrust),
//     .uncache	(1'b0),
//     .i_raddr	(i_ic_raddr),

//     .axi_write	(1'b0),
//     .dirty_addr	(32'b0),
// 	.i_waddr	(32'b0),
//     .i_wdata	(128'b0),
// 	.wstrb_t	(8'b0),

// 	.wdone		(),
//     .rdone		(),
// 	.cache_wdata(o_ic_cache_wdata),
//     .wen 		(o_ic_cache_wen),
//     .i_awready	(ic_awready),              
//     .o_awvalid 	(ic_awvalid),
//     .o_awaddr 	(ic_awaddr),
//     .o_awid 	(ic_awid),
//     .o_awlen 	(ic_awlen),
//     .o_awsize 	(ic_awsize),
//     .o_awburst 	(ic_awburst),
//     .i_wready	(ic_wready),                
//     .o_wvalid 	(ic_wvalid),
//     .o_wdata 	(ic_wdata),
//     .o_wstrb 	(ic_wstrb),
//     .o_wlast 	(ic_wlast),
//     .o_bready 	(ic_bready),                
//     .i_bvalid	(ic_bvalid),
//     .i_bresp	(ic_bresp),                 
//     .i_bid		(ic_bid),
// 	.o_araddr	(ic_araddr),
// 	.o_arid		(ic_arid),
// 	.o_arlen	(ic_arlen),
// 	.o_arvalid	(ic_arvalid),
// 	.i_arready	(ic_arready),
//     .o_arsize	(ic_arsize),
//     .o_arburst	(ic_arburst),
// 	.i_rdata	(ic_rdata),
// 	.i_rid		(ic_rid),
// 	.i_rresp	(ic_rresp),
// 	.i_rlast	(ic_rlast),
// 	.i_rvalid	(ic_rvalid),
// 	.o_rready	(ic_rready)

// );

// ysyx_050369_cache2axi dcache2axi(
// 	.clk		(clk),    // Clock
// 	.rst		(rst),  // Asynchronous reset active low
// 	.size_t		(i_dc_size_t),
//     .axi_read 	(i_dc_axi_read),
//     .unbrust	(i_dc_unbrust),
//     .uncache	(i_dc_uncache),
//     .i_raddr	(i_dc_raddr),
//     .axi_write	(i_dc_axi_write),
//     .dirty_addr	(i_dc_dirty_addr),
// 	.i_waddr	(i_dc_waddr),
//     .i_wdata	(i_dc_wdata),
// 	.wstrb_t	(i_dc_wstrb_t),
	
// 	.wdone		(o_dc_wdone),
//     .rdone		(o_dc_rdone),
// 	.cache_wdata(o_dc_axi_data),
//     .wen 		(o_dc_axi_wen),
//     .i_awready  (dc_awready),              
//     .o_awvalid  (dc_awvalid),
//     .o_awaddr   (dc_awaddr),
//     .o_awid     (dc_awid),
//     .o_awlen    (dc_awlen),
//     .o_awsize   (dc_awsize),
//     .o_awburst  (dc_awburst),
//     .i_wready   (dc_wready),                
//     .o_wvalid   (dc_wvalid),
//     .o_wdata    (dc_wdata),
//     .o_wstrb    (dc_wstrb),    
//     .o_wlast    (dc_wlast),
//     .o_bready   (dc_bready),                
//     .i_bvalid   (dc_bvalid),
//     .i_bresp    (dc_bresp),                 
//     .i_bid      (dc_bid),
//     .i_arready  (dc_arready),                  
//     .o_arvalid  (dc_arvalid),   
//     .o_araddr   (dc_araddr),
//     .o_arid     (dc_arid),
//     .o_arlen    (dc_arlen),
//     .o_arsize   (dc_arsize),
//     .o_arburst  (dc_arburst),
//     .o_rready   (dc_rready),                  
//     .i_rvalid   (dc_rvalid),                
//     .i_rresp    (dc_rresp),
//     .i_rdata    (dc_rdata),
//     .i_rlast    (dc_rlast),
//     .i_rid      (dc_rid)

// );
//     reg [1:0]   read_choose;
//     wire        arvalid  ;
//     wire [31:0] araddr   ;
//     wire [3:0]  arid     ;
//     wire [7:0]  arlen    ;
//     wire [2:0]  arsize   ;
//     wire [1:0]  arburst  ;

//     always @(posedge clk) begin
//         if (rst) begin
//             read_choose <= 'b0;
//         end
//         else begin
//             if (dc_arvalid && ~read_choose[1]) begin
//                 read_choose[0] <= 'b1;
//             end
//             else if (dc_rready&&dc_rvalid&&dc_rlast) begin
//                 read_choose[0] <= 'b0;
//             end
//             else if (ic_arvalid) begin
//                 read_choose[1] <= 'b1;
//             end
//             else if (ic_rready&&ic_rvalid&&ic_rlast) begin
//                 read_choose[1] <= 'b0;
//             end
//         end
//     end

//     assign arvalid      = read_choose[0]?dc_arvalid :(read_choose[1]?ic_arvalid:'b0 ); 
//     assign araddr       = read_choose[0]?dc_araddr  :(read_choose[1]?ic_araddr :'b0 );
//     assign arid         = read_choose[0]?dc_arid    :(read_choose[1]?ic_arid   :'b0 );
//     assign arlen        = read_choose[0]?dc_arlen   :(read_choose[1]?ic_arlen  :'b0 );
//     assign arsize       = read_choose[0]?dc_arsize  :(read_choose[1]?ic_arsize :'b0 );
//     assign arburst      = read_choose[0]?dc_arburst :(read_choose[1]?ic_arburst:'b0 );

// //read addr
//     //master
//     assign dc_arready = i_sl_arready&& read_choose[0]; 
//     assign ic_arready = i_sl_arready&& read_choose[1] && ~read_choose[0]; 
//     //slave 
//     assign o_sl_arvalid = arvalid ;
//     assign o_sl_araddr  = araddr  ;
//     assign o_sl_arid    = arid    ;
//     assign o_sl_arlen   = arlen   ;
//     assign o_sl_arsize  = arsize  ;
//     assign o_sl_arburst = arburst ;

// //read data
//     //master
//     assign ic_rdata   = i_sl_rdata;
//     assign ic_rid     = i_sl_rid;
//     assign ic_rresp   = i_sl_rresp;
//     assign ic_rlast   = i_sl_rlast;
//     assign ic_rvalid  = i_sl_rvalid&&read_choose[1];
//     assign dc_rdata   = i_sl_rdata;
//     assign dc_rid     = i_sl_rid;
//     assign dc_rresp   = i_sl_rresp;
//     assign dc_rlast   = i_sl_rlast;
//     assign dc_rvalid  = i_sl_rvalid&&read_choose[0];
//     //slave 
//     assign o_sl_rready  = (ic_rready&&read_choose[1]) || (dc_rready&&read_choose[0]) ;

// //write addr
//     //master
//     assign dc_awready  = i_sl_awready;
//     //salve
//     assign o_sl_awaddr   = dc_awaddr;
//     assign o_sl_awid     = dc_awid;
//     assign o_sl_awlen    = dc_awlen;
//     assign o_sl_awsize   = dc_awsize;
//     assign o_sl_awburst  = dc_awburst;
//     assign o_sl_awvalid  = dc_awvalid;
//     assign ic_awready  = 'b0;

// //write data
//     //master
//     assign dc_wready   = i_sl_wready;
//     //salve
//     assign o_sl_wdata    = dc_wdata;
//     assign o_sl_wstrb    = dc_wstrb;
//     assign o_sl_wlast    = dc_wlast;
//     assign o_sl_wvalid   = dc_wvalid;
//     assign ic_wready   = 'b0;
// //write rep
//     //master
//     assign dc_bvalid   = i_sl_bvalid;
//     assign dc_bresp    = i_sl_bresp;
//     assign dc_bid      = i_sl_bid;
//     //slave
//     assign o_sl_bready   = dc_bready ;
//     assign ic_bvalid   = 'b0;
//     assign ic_bresp    = 'b0;
//     assign ic_bid      = 'b0;



endmodule